In general, fabrication of a semiconductor integrated circuit begins with a definition of a specific function and circuit design to accomplish the function. Such a circuit design process includes a circuit layout (chip layout) step, which is performed with sophisticated computer-aided design (CAD) systems.
In a semiconductor integrated circuit, a power signal may be changed in level due to noise omitted by other circuits. A circuit that operates with a lower level of voltage, such as a differentially-operating type of circuit, may be substantially affected by the noise and have some errors. For reducing the affect of the noise, in a conventional chip layout, a plurality of power supplies are employed to realize a multi-power-supply structure, or a capacitance pattern is inserted in the layout of the integrated circuit. The conventional chip layout is logically verified using a four-terminal transistor model to check connection of all the nodes.
According to the conventional chip layout, for realizing the multi-power-supply structure, a semiconductor substrate and a metal wiring pattern are each required to be divided. Otherwise, a capacitance pattern is required to be inserted in the chip layout. Therefore, the conventional chip layout is not applicable to an LSI chip with a pre-formed mask pattern, such as a gate-array. When the capacitance pattern is inserted in the chip layout, the area of the chip becomes larger. Further, in a process for making a mask pattern, it is required to generate information indicating that a part of the circuit is provided with an extra power supply. And, it is required that an operator carry out additional work.
According to the conventional method for verifying the chip layout, it is impossible to detect an error in which a signal node is connected to an unconnected semiconductor substrate, provided with no power supply. In addition, it takes a long time to detect a location where a short circuit is made among a plurality of signal nodes.